UniPCemu build 2018/04/14 11:41 is now live!

Now, UniPCemu is back with another update! From small things like bugfixes to large things like timing improvements and improved functionality!

  • SDL2 has been updated to version 2.0.8
  • The common emulator framework has been updated with lots of small and big bugfixes.
  • Fixed LEA parameter order.
  • Fixed Debugger register MOV instructions to use debugger registers instead of control registers.
  • Fixed remaining 80386+ instructions to use proper memory operands when required.
  • Modified 80386 0F opcodes to use the instruction lookup table.
  • Modified the 80486+ opcodes to use the instruction lookup table.
  • Adjusted 80386+ special registers(CRn,DRn,TRn) to use the instruction lookup tables correctly.
  • ATA-1: drive seek complete is always set, except when seeking. ATAPI has a different meaning(service bit, thus always cleared).
  •  Improved ready for command seek status on hard disks.
  • Applied defaults settings for ATA/ATAPI reset commands.
  • Fixed reversed defaults setting applying on IDE drives.
  • Fixed PS/2 keyboard disable/enable of it's port vs keyboard reset.
  • Enabled Compaq Deskpro 386 built-in memory and RAM relocation to work properly.
  • Simplified DMA mode register handling.
  • Made the DMA controller cases handle all possible cases.
  • Improved DMA with the Verify transfer from Bochs
  • Improved DMA status register, with adding the DREQ signal to the high bits of the Status Register, to allow software to detect requests(that aren't acnowledged).
  • Removed the last MMU invalid address detection.
  • Improved x86 real-mode IRET to be cycle-accurate, using the BIU.
  • Fixed x86 real-mode IRET to work properly.
  • Fixed x86 real mode IRET to POP correctly with 32-bit operand size.
  • Improved 8042 RAM and input defaults.
  • 8042 self test disables the first PS/2 port on hardware.
  • Improved handling of PCI IDE harddrive configurations.
  • Improved RETF instructions.
  • Reversed 32-bit RETF to pop 16-bit CS correctly with 32-bit stack again.
  • Removed 80386 extension of opcode EB: it's the same as the 8086+ version.
  • Implemented parallel port I/O timing.
  • Added likelyness to various timed hardware(optimization improvement).
  • Improved x86 opcode 83h zero-extending the immediate value.
  • Improved x86 real-mode CALLF to be using the BIU for cycle-accuracy.
  • Improved cycle-accuracy of RETF instruction to use the BIU to retrieve it's data from memory in a cycle-accurate way.
  • Improved FNINIT opcode support.
  • Implemented proper #NM exception support.
  • Added proper implementation of #NM coprocessor exception.
  • Implemented #MF(Coprocessor Error) handler.
  • Improved 80386 FWAIT exception handling.
  • Implemented the new 80287+ FWAIT instruction.
  • Improved disassembly of the undocumented FPU instructions when not raising a fault.
  • Fixed XLAT 16-bit address wrapping.
  • Resolved x86 FWAIT exception that doesn't need to trigger.
  • Improved x87 FWAIT instruction according to documentation.
  • Improved x86 LEAVE instruction to work properly, handling (E)SP correctly.
  • Improved x86 LEAVE instruction to assign (E)SP only once, during it's first execution phase.
  • Improved x86 ENTER and LEAVE instructions with different Stack Operand sizes.
  • Improved ENTER instruction with 16-bit and 32-bit operand sizes vs Stack sizes.
  • Improved FDC Seek/Recalibrate to finish immediately when already on the right track.
  • Finishing a seek doesn't set the FDC idea of the current cylinder, this is determined by the seeking itself.
  • FDC Sense Interrupt gives the FDC's idea of the current cylinder, not the physical one.
  • Improved FDC Seek/Recalibrate vs Disk Changed bit.
  • Resetting the FDC doesn't affect the physical drives to track 0.
  • Improved FDC read/write/format not setting any cylinder data, instead just verifying it before accessing the disk data(like a real FDC).
  • Implemented simple floppy implied seek support without timing.
  • Switching when increasing FDC sectors to side 0 doesn't change the cylinder to use.
  • Improved FDC relative seeking vs MT bit.
  • Resetting the FDC doesn't reset the current cylinder information.
  • Improved FDC Configuration defaults.
  • Improved unconnected floppy drives to fail seeking the heads always(timing out when possible).
  • Fixed opcode 86/87h XCHG parameter order to be correct(reg,r/m).
  • Fixed FDC seek to non-zero track being completed status correctly.
  • Register LOCK prefix checks are to be performed on lockable r/m operands only. It's never applied to the reg operand, since it's not lockable(processor internal).
  • Optimized CPU debugger and fault unlikeliness(speed optimization).
  • Flag operation unlikely to #GP fault(speed optimization).
  • Updated modem listen port setting information in the settings file.
  • Changed the Android default modem listen port to 65523 instead of 23.
  • Improved 80286 not supporting an 8-bit BUS and improved documentation.
  • Fixed 80386 not checking the required internal instruction step before checking memory parameters for faults.
  • Fixed 8086 vs 80386 difference.
  • Added type conversion to opcode 6A(PUSH immediate signed byte).
  • Improved memory checking on opcodes 69/6B IMUL on 80186+ and 80836+ CPUs.
  • Pseudo protection fault during Virtual 8086 mode only happens when the segment limit raises a fault.
  • Fixed cycles being applied for 32-bit CWDE/CDQ instructions.
  • Improved handling of segment writes and aborts during CALL instructions and added support for aborting the segmentation write.
  • Improved x86 CALLF timings.
  • Fixed XT PPI interface to work properly again.
  • Improved 8042/PPI response to the keyboard clock lines and acnowledge bits in PPI port 61/KB Controller Port B.
  • Fixed XT keyboard clock line to properly disable/enable the line when requested and reset the connected keyboard.
  • Reversed the XT PPI according to documentation.
  • Fixed initial System Control Port B error value to be not set.
  • Improved PPI 62 vs System Control Port B on XT architectures.
  • Improved input locking behaviour on the emulator core.
  • Improved 80486/80386/80286 LOADALL (un)support(ed).
  • Fixed 80286 GDTR/IDTR register loading shifting and masking correctly during the 80286 LOADALL.
  • Fixed 80386 LOADALL loading EFLAGS, EDX and ECX correctly.
  • Fixed 80286 LOADALL loading DX and CX correctly.
  • Improved real mode compatibility loading non-CS registers.
  • Improved comments and simplified Virtual 8086 mode noncallgate_info field assignment.
  • Improved CPL support changing of CPL through non-call gates(not changing CPL).
  • Fixed various compiler and code analysis warnings using MinGW and Visual Studio.
  • Fixed overflow check on the MMU_directptr function.
  • Added support for double percision to be adjusted to single percision or long double percision, at a cost of reduced accuracy.
  • Loading System Descriptors in CS is illegal.
  • Simplified active NULL descriptor checks(not using the segment register, instead using the present bit only).
  • Removed cases already handled further up the code(Privilege level and data in code segment checks).
  • CPL when entering protected mode is determined by the SS segment's DPL.
  • Improved CPL support being based on the SS segment DPL with LOADALL.
  • Improved floppy clearing internal memory buffers to use proper pointers.
  • Improved IBM AT and up DMA clock running at half the CPU clock speed when using an IBM AT or higher.
  • Modified IBM AT BUS waitstates to 1 cycle to get a 6 or 12(word using byte transactions) cycle BUS transaction, resulting in the proper documented speed.
  • DMA runs at half CPU clock instead of whole CPU clock on AT architecture.
  • DMA doesn't need locks, since it doesn't use any special lockable objects.
  • Fixed the FDC rate selection lookup tables for step rates to be correct.
  • Improved segment overrides with string instructions, with DS being overridable and ES not being overridable.
  • Improved load to segment register from modr/m to inhabit interrupts and use the parameter table correctly(instead of overwriting on 80186+).
  • Improved check for popping into SS with the 16-bit 8F opcode.
  • Improved segment register loading with invalid task register value being loaded.
  • Improved task register loading faults to be more correct.
  • Improved handling of idle when loading the task register.
  • Fixed saving a correctly loaded TSS descriptor back to RAM.
  • Improved call gate RPL and CPL settings after executing the gate.
  • Improved switching privilege levels between real/protected/Virtual 8086 modes.
  • Improved 80286+ support switching tasks and loading the LDTR.
  • Improved task switching LDTR descriptor loading VS Page faults.
  • Improved clearing memory using memset, not using malformed pointers anymore(causing crashes).
  • Fixed task switching to finish correctly after completing the task switch.
  • Fixed task switching stack fault when pushing the error code.
  • Cleaned up the multitasking CPU support a bit with the new loading method.
  • Fixed an Android redirect file parsing bug(which was using a malformed pointer(causing crashes)).
  • A reboot is always required when changing video cards, not having anything to do with SVGA or not(only memory size redetection does).
  • Fixed 286+ timings lookup table generation when using a CPU that's older than the 80286(causing crashes due to index underflow).
  • Improved handling of writes to segment registers to not always become the value that's loaded directly, instead of always loading the literal value that's loaded.
  • Cleaned up CMPSB and STOSW/D instructions redundant stepping.
  • Default segment register isn't to be reapplied when repeating instructions using the REP(N/NZ) instruction prefixes.
  • Improved option text on the main Settings menu.


UniPCemu.apk 3 MB
Apr 14, 2018
UniPCemu_PSP.zip 668 kB
Apr 14, 2018
UniPCemu_win32.zip 1 MB
Apr 14, 2018
UniPCemu_win64.zip 1 MB
Apr 14, 2018

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